Recently, SOI wafers increasingly have been used in very-large scale integration (VLSI) or ultra-large scale integration (ULSI) of semiconductor devices. An SOI wafer typically has a layer of silicon on top of a layer of an insulator material. In an SOI integrated circuit, essentially complete device isolation may be achieved using conventional device processing methods by surrounding each device, including the bottom of the device, with an insulator. One advantage which SOI wafers have over bulk silicon wafers is that the area required for isolation between devices on an SOI wafer is less than the area typically required for isolation on a bulk silicon wafer.
SOI wafers offer other advantages over bulk silicon technologies as well. For example, SOI wafers offer a simpler fabrication sequence compared to a bulk silicon wafer. Devices fabricated on an SOI wafer may also have better radiation resistance, less plasma-induced damage, and less cross-talk than devices fabricated on bulk silicon wafers.
Devices within integrated circuits are very sensitive to the presence of even minute concentrations of some impurities. For example, metals, such as copper, nickel, silver, gold, or iron, within the active region of a device typically degrade several device characteristics, including leakage current and oxide breakdown voltage. These and other metals rapidly diffuse through bulk silicon at temperatures typical of semiconductor device fabrication processes. Most all the transition metals have been reported as possible contaminants. Such impurities in the active region of the SOI wafer migrate out of the active region more slowly than they migrate in bulk silicon because the insulation region tends to retard impurities in the active layer from diffusing into the bulk silicon beneath the insulation region. Some impurities which have migrated to, but have been retarded by, the insulation region may re-migrate into the active region during subsequent processing steps. Accordingly, SOI wafers are subject to device and reliability problems caused by the presence of impurities that remain in the active regions.
Methods of gettering a silicon substrate are well known. Gettering is used to remove impurities or contaminants from regions of the circuit where their presence would degrade device performance. It is desirable to reduce the presence of such impurities or contaminants in the active regions in order to reduce, for example, reverse junction leakage, improve bipolar transistor gain, and increase refresh time in dynamic metal oxide semiconductor (MOS) memories.
In the manufacture of SOI integrated circuits from an SOI wafer, one of the final process steps is to dice the wafer, which contains many dies in an array, into a plurality of individual dies. In order to perform the dicing step, the wafer is divided along portions of the wafer commonly referred to as dicing rails, saw lanes or scribe lanes. When the dicing step is performed on an SOI wafer, a portion of the scribe lane remains at the perimeter of each newly separated die. The scribe lane area is available for formation of gettering sites into which contaminants resulting from cutting, packaging and/or aging may be gettered. Prior art scribe lane gettering methods, such as that of U.S. Pat. No. 6,093,624, relied upon gettering into strain areas formed in the silicon active layer of the SOI wafer when LOCOS areas were formed in the scribe lanes. However, this method provides only small gettering areas of uncontrolled size. In addition, such gettering sites may not effectively trap impurities, allowing the impurities to re-migrate to the active regions. Thus, a need remains for a scribe lane gettering method which provides a significantly increases quantity and quality of gettering sites.